A1.1.5 · Computer hardware and operation
The fetch–decode–execute cycle
By the end you can
Describe each stage of the cycle, naming the registers and buses used at every step, and trace a short program through it.
A program is just a list of instructions sitting in memory, one after another. Nothing happens until the processor goes and gets them. The does this with one simple loop, repeated billions of times every second: fetch the next instruction from memory, decode it to work out what it means, and execute it. Then it does the same again for the next one. This loop is the .
Each step of the cycle moves one value along one wire, and every step happens on a tick of the CPU's . By the end of this section you will be able to say exactly which register and which bus is used at every step, which is what exam questions on this topic ask for.
The cast: five registers and three buses#
You met these in A1.1.1. In the cycle each one has a precise job. are tiny, very fast stores inside the CPU, each holding a single value.
| Register | Holds | Used |
|---|---|---|
| the address of the next instruction | start of every fetch; changed by branches | |
| the address being read or written | every memory access | |
| the value travelling to or from memory | every memory access | |
| the instruction being worked on | end of fetch, through decode and execute | |
| the value being worked on, and results | execute (loads, ALU results, stores) |
Values move between the CPU and memory along three . The carries an address one way, from the CPU to memory. The carries the contents of that address, in either direction. The carries the signals that say what should happen, such as read or write.
Fetch: getting the next instruction#
PC → MAR
The program counter holds the address of the next instruction. It is copied into the MAR, and the MAR puts that address on the address bus.Memory → MDR
The control unit sends a read signal on the control bus. Memory sends back the contents of that address along the data bus, and they land in the MDR.MDR → IR, and PC + 1
The instruction is copied into the instruction register, where it stays while it is decoded and executed. The program counter goes up by 1, ready for the next fetch.
Decode: working out what it means#
The now looks at the instruction in the IR. An instruction has two parts: the , which says which operation to do (load, add, store, jump...), and the , which says what to do it to, usually a memory address. Having decoded it, the control unit gets ready to send the control signals the instruction needs.
In the model CPU below every instruction is a 3-digit number: the first digit is the opcode and the last two are the address. So 505 decodes as opcode 5 = load, address 05. Real processors do the same thing with binary patterns, but the idea is identical.
Execute: doing it#
What happens now depends on the instruction. Three patterns cover almost everything:
- Load or calculate (LDA, ADD, SUB): the operand's address goes into the MAR and out on the address bus, a read signal goes out, and the value comes back into the MDR. A load copies it into the ; an add or subtract passes it and the accumulator through the , and the result goes back into the accumulator.
- Store (STA): the address goes into the MAR, the accumulator's value goes into the MDR, and a write signal sends it along the data bus into memory.
- Branch (BRA, BRZ, BRP): the operand is copied into the PC, so the next fetch comes from somewhere else. A conditional only does this if its test passes. This is how loops and decisions work.
Then the cycle starts again with the next fetch.
No input needed. Loads 17, adds 25, stores and outputs 42. The best one to step through first.
Press Next step to start the first fetch. Each press moves one value along one wire.
Program
- // Add two numbers kept in memory
- 00 LDA first◀
- 01 ADD second
- 02 STA total
- 03 OUT
- 04 HLT
- 05first DAT 17
- 06second DAT 25
- 07total DAT 0
Input
empty
Output
nothing yet
RAMaddresses 00–19 of 100
current instruction on the address bus data
Tracing a program by hand#
Exam questions often give you a short program and ask what is in the registers at some point. The method is a trace table: one row per instruction, recording the registers after it has finished. Here is the first program from the simulator, traced. Check each row against the simulator using Whole instruction.
| Address · instruction | PC | MAR | MDR | IR | AC | Also |
|---|---|---|---|---|---|---|
| 00 · LDA 05 | 1 | 05 | 017 | 505 | 17 | |
| 01 · ADD 06 | 2 | 06 | 025 | 106 | 42 | |
| 02 · STA 07 | 3 | 07 | 042 | 307 | 42 | wrote 42 to 07 |
| 03 · OUT | 4 | 03 | 902 | 902 | 42 | output 42 |
| 04 · HLT | 5 | 04 | 000 | 000 | 42 | stopped |
Notice three things that catch people out:
- The PC is always one ahead of the instruction just executed, because it was increased during the fetch.
- The MAR and MDR keep their last values. After OUT, which never goes to memory in its execute stage, the MAR still holds the address it was fetched from.
- The IR holds the whole instruction (opcode and address), not just the opcode.
Which bus, when#
| Moment | Address bus | Data bus | Control bus |
|---|---|---|---|
| Fetching an instruction | address from the PC (via MAR) | the instruction, memory → MDR | read |
| Loading a value (LDA, ADD, SUB) | operand address (via MAR) | the value, memory → MDR | read |
| Storing a value (STA) | operand address (via MAR) | the value, MDR → memory | write |
| Branching, decoding, ALU work | not used | not used | internal signals only |
Real processors
The model here keeps the idea and drops the detail. Real CPUs have many more registers and hundreds of instructions encoded in binary, and they overlap the stages of several instructions at once (that is pipelining, in A1.1.6 for HL). The exam will not ask you about this model's instruction codes: what it asks about is the cycle itself, and that is exactly the same.
Check yourself
Registers, buses and the cycle
Quick questions, made fresh every time and marked here. Do a few until they feel easy.
Exam practice
Paper 1-style questions
6 questions · 22 marks
Write your answer as you would in the exam, then show the mark points and tick each one your answer made. These are our own questions in the style of the exam, not past-paper questions.
1.Outline the role of the program counter (PC) in the fetch–decode–execute cycle.
[2]Outline: A brief account: the main points, without much detail.
2.Describe the fetch stage of the fetch–decode–execute cycle.
[4]Describe: A detailed account: say what happens, step by step if it is a process.
3.Explain why the CPU uses both a memory address register (MAR) and a memory data register (MDR) when it reads from memory.
[3]Explain: Give reasons: say what happens AND why, or how one thing causes another.
4.The program below starts with the PC at 0. State the values in the PC, MAR, MDR and accumulator just after the instruction at address 1 has been executed.
[4]00 LDA 6 01 SUB 7 02 STA 8 03 HLT 04 DAT 0 05 DAT 0 06 DAT 50 07 DAT 18 08 DAT 0
Trace: Follow the program or process step by step, recording the values.
5.Describe how the three buses are used when the CPU executes an instruction that stores the accumulator in memory.
[3]Describe: A detailed account: say what happens, step by step if it is a process.
6.To what extent does doubling a CPU’s clock speed double the speed at which it runs programs?
[6]To what extent: Argue for and against, then say how far you agree, with your reasons.
Past papers
Old exam questions on this topic
From HL Paper 1, May 2014 to November 2025. These papers were set on the previous syllabus, so the wording may differ from today's exam, but the topic is the same. Find the questions and markschemes in your school's past-paper pack.
| Paper | Question | Marks | About |
|---|---|---|---|
| May 2018 | 2 | 2 | The MDR in the machine instruction cycle |
| November 2018 | 8(b) | 4 | Data and address buses in the cycle |
In a nutshell
- A program is a list of instructions held in memory. The CPU runs it by repeating one cycle: fetch, decode, execute.
- Fetch: PC → MAR, address on the address bus, read signal on the control bus, instruction back on the data bus into the MDR, then MDR → IR. The PC goes up by 1 during the fetch.
- Decode: the control unit splits the instruction in the IR into its opcode (what to do) and operand (usually an address) and prepares the control signals.
- Execute: the instruction is carried out. Loads and stores use the buses again; ADD and SUB use the ALU and the accumulator; a branch puts a new address in the PC.
- The address bus only carries addresses from the CPU to memory. The data bus carries data both ways. The control bus carries signals such as read, write and the clock.
- In an exam, name the registers and buses at every step, in order.